FIG. 1 schematically shows a portion of a component combining a VDMOS transistor and a logic circuit. This component includes an N-type substrate generally formed of an N-type epitaxied layer 1 formed on an N.sup.+ -type substrate 2. A power transistor is formed in the right-hand portion and a logic well is formed in the left-hand portion.
The power transistor includes a set of identical cells connected to one another, such as cell 3. Each cell includes a P-type well 4, the central portion 5 of which is more heavily doped. An N-type ring 6 is formed in the upper portion of the well. The portion separating the external periphery of the N-type ring from the external periphery of the P-type well is coated with an insulated gate 8. The N-type ring 6, as well as central portion 5 of the well are coated with a metallization 9. All gates 8 are connected to a gate terminal G and all metallizations 9 are connected to a source terminal S. The rear surface of the structure is coated with a drain metallization D. Thus, when a gate signal is applied, a current is likely to flow from terminal D to terminal S. More specifically, the current likely flows from N regions 1 and 2 to N region 6, via a channel formed under the insulated gates. This structure is generally used so that the drain is biased at a positive potential with respect to the source.
Although identical "cells" have been mentioned here-above, the power transistor can have a digited structure. Regions 6 are then not "rings". This vocabulary will however be kept hereafter to simplify the discussion.
Logic circuits are formed in one or several wells 10. An elementary MOS transistor having drain, source, and gate terminals d, s, and g has been shown in the well 10. This is only an example of component likely to be formed in a logic well.
In some applications, for example in switched mode power supplies, a high voltage gradient is likely to appear between the drain and the source of the MOS power transistor during a phase of switching to the off state.
FIG. 2 shows an example of a switched-mode power supply circuit. An input voltage V.sub.IN is applied to a primary 20 of a transformer, a secondary 21 of which is connected to a capacitor 22 via a diode 23. An output voltage V.sub.OUT is available across capacitor 22. The second terminal of primary 20 is connected to the supply ground via an integrated component 25 including a vertical MOS power transistor TP and a logic circuit 27. This logic circuit includes a terminal connected to the drain terminal of the power transistor, corresponding to the rear surface of the component of FIG. 1, a terminal connected to the ground and at least one input terminal 28 receiving control signals. This logic circuit 27 is especially meant for controlling the gate of the power transistor.
The operation of a switched-mode power supply is well known by those skilled in the art. It consists of periodically switching power transistor TP. Upon each switching to the off-state of power transistor TP, there is a high power-up, which is effectively desired to be as quick as possible. Even if no parasitic component intervenes and the voltage across power transistor TP does not exceed the normal maximum voltage of the circuit, integrated components of the type of that in FIG. 1 appear to be damaged under certain circumstances. This phenomenon is not explained a priori and it is the contribution of the present invention to have analyzed this phenomenon, to have found its cause, and to have brought a remedy thereto.